1. Field of the Invention
The present invention generally relates to information-processing devices, information-processing methods, and processors, and particularly relates to an information-processing device, an information-processing method, and a processor which perform a transaction-retry operation.
2. Description of the Related Art
As large-scale servers are more widely used, there are expectations that multi-processor systems having a high data-processing capacity and a sufficient reliability will soon be available.
One of the most important factors that control performance of multi-processor systems is speed of a system bus. In order to increase speed of a system bus, the system bus may be pipelined.
A pipelined system bus can increase throughput of the bus. When error occurs, however, a flow of the pipeline operation is disturbed, resulting in a drop in performance. There are various schemes that are developed to avoid the performance drop at the time of error.
One of such schemes is a retry operation. The retry operation resumes a failed process by reissuing an address transaction that caused an error. Since the retry operation is a very important factor that controls performance of a multi-processor system, a reliable and high performance retry operation is necessary.
A pipelined system bus is configured such that an address transaction is divided into a plurality of stages, and that buses corresponding to the respective stages can process transactions independently of each other. Namely, pipelined transactions are performed.
Among various multi-processor systems, multi-processor systems of a shared memory type are regarded as that of a mainstream. The multi-processor systems of a shared memory type have a plurality of processors accessing a shared memory, so that address snooping is performed across the entire system, thereby maintaining coherency.
In such systems, two types of errors are observed. One is an error caused by a system failure or the like, and the other is an error that frequently occurs during a routine or normal operation because of address conflict or the like.
The address conflict occurs when two transactions accessing the same address are successively issued, and results of the first transaction are not available when the second transaction needs to refer them.
There are two methods to cope with this situation. The first method is to suspend the bus until the second transaction can be performed. The second method is to terminate the second transaction and to issue the same address to the bus.
The second method is called an address retry method, and a mechanism for performing an address retry operation is called an address-retry mechanism. Most of the related-art multi-processor systems are provided with an address-retry mechanism in order to prevent a decrease in system performance.
FIG. 1 is a block diagram of a related-art multi-processor system.
A multi-processor system 1 includes processors 2-1 through 2-N, a shared memory 3, an input-output device 4, a bus-control unit 5, and a system bus 6.
The processors 2-1 through 2-N perform operations according to instructions.
The memory 3 is connected to the N processors 2-1 through 2-N via the system bus 6, and is accessible from the N processors 2-1 through 2-N. The memory 3 is shared by the processors 2-1 through 2-N.
The input-output device 4 is comprised of a keyboard, a mouse, a display, a printer, a communication device, and the like. The input-output device 4 attends to data inputting/outputting, instruction inputting, processing result inputting/outputting.
The bus-control unit 5 is connected to the N processors 2-1 through 2-N and the input-output device 4, and controls the right to use the bus 6. The bus 6 is used for data transfer between the N processors 2-1 through 2-N, the memory 3, and the input-output device 4.
FIG. 2 is a block diagram showing a configuration of a processor shown in FIG. 1.
A processor 2-X is one of the N processors 2-1 through 2-N. The processor 2-X and the bus-control unit 5 are connected via the bus 6. The bus 6 includes an address bus 11, an address bus 12, a status bus 13, a status bus 14, and a data bus 15.
The address bus 11 transfers addresses from the processor 2-X to the bus-control unit 5. Addresses transferred through the address bus 11 are issued by the processor 2-X for transaction purposes, for example.
The address bus 12 transfers addresses from the bus-control unit 5 to the processor 2-X. Addresses transferred through the address bus 12 are arbitrated by the bus-control unit 5 so that permission to use the bus 6 is granted to these addresses, for example.
The status bus 13 delivers statuses of the processor 2-X from the processor 2-X to the bus-control unit 5. The statuses delivered by the status bus 13 include results of cache snooping performed by the processor 2-X.
The status bus 14 supplies statuses from the bus-control unit 5 to the processor 2-X. The statuses carried through the status bus 14 include combined results of cache snooping for the N processors 2-1 through 2-N. The data bus 15 transfers data according to the results of the cache snooping.
In the following, a related-art address-transaction process will be described.
The processor 2-X includes an arithmetic-logic unit 21, an address-control unit 22, and a snooping-control unit 23.
The arithmetic-logic unit 21 attends to data processing, and requests an address transaction according to the results of the data processing. The address-control unit 22 issues an address in response to the address-transaction request made by the arithmetic-logic unit 21.
The address-control unit 22 includes a queue-issuing unit 22a, a retry-control unit 22b, and a counter unit 22c. The queue-issuing unit 22a issues an address in accordance with the address transaction.
The retry-control unit 22b is connected to the arithmetic-logic unit 21, the snooping-control unit 23, and the bus-control unit 5. The retry-control unit 22b controls the queue-issuing unit 22a according to retry instruction sent from the snooping-control unit 23.
When this happens, the retry-control unit 22b has a retry count and/or a time limit recorded therein as they are sent from the arithmetic-logic unit 21. The counter unit 22c supplies a retry count and/or a time that are counted therein to the retry-control unit 22b. The retry-control unit 22b repeats a retry operation until the retry count or the time supplied from the counter unit 22c becomes the retry count or the time limit stored therein.
The retry-control unit 22b further stores therein a status of use of the bus 6 that is reported from the bus-control unit 5. The retry-control unit 22b controls frequency of retry operations according to the status reported by the bus-control unit 5.
The counter unit 22c counts a retry count, and/or marks time. The retry-control unit 22b refers to the retry count and/or the marked time supplied from the counter unit 22c, and limits the retry operations to a predetermined number or to be within the predetermined time period.
The snooping-control unit 23 obtains a cache status from the bus-control unit 5 in response to an address. The snooping-control unit 23 controls data transfer in response to the cache statuses of the entire system that are reported from the bus-control unit 5, and issues an instruction for an address retry.
In what follows, operation at the time of address transaction will be described.
At a first step, the arithmetic-logic unit 21 of the processor 2-X issues an address-transaction request. The address transaction request issued by the arithmetic-logic unit 21 is supplied to the queue-issuing unit 22a of the address-control unit 22.
At a second step, the queue-issuing unit 22a issues an address in response to the address transaction request from the arithmetic-logic unit 21. The address issued by the queue-issuing unit 22a is supplied to the bus-control unit 5.
At a third step, the bus-control unit 5 supplies the address sent from the processor 2-X to the address bus 12 of the processors 2-1 through 2-N.
At a fourth step, the processors 2-1 through 2-N obtain cache statuses with respect to the address indicated by the bus-control unit 5.
At a fifth step, the bus-control unit 5 combines the cache statuses reported from the processors 2-1 through 2-N, thereby obtaining the system-overall cache statuses.
At a sixth step, the bus-control unit 5 supplies the system-overall cache statuses to the processors 2-1 through 2-N. The processor 2-X receives the system-overall cache statuses from the bus-control unit 5.
At a seventh step, the processor 2-X controls data transfer based on the system-overall cache statuses reported from the bus-control unit 5.
The first through seventh steps are performed with respect to each transaction generated by the processors 2-1 through 2-N. The first through seventh steps are carried out in a pipeline manner to achieve multiple and simultaneous processes, thereby improving processing speed.
FIG. 3 is an illustrative drawing for explaining related-art pipeline processes.
In FIG. 3, transactions AT1 through AT3 are shown. The transaction AT1 is comprised of a second step S2 performed at a time t1, a third step S3 performed at a time t2, a fourth step S4 performed at a time t3, a fifth step S5 performed at a time t4, a sixth step S6 performed at a time t5, and a seventh step S7 performed at a time t6. The transaction AT2 is comprised of a second step S2 performed at the time t2, a third step S3 performed at the time t3, a fourth step S4 performed at the time t4, a fifth step S5 performed at the time t5, a sixth step S6 performed at the time t6, and a seventh step S7 performed at a time t7. The transaction AT3 is comprised of a second step S2 performed at the time t3, a third step S3 performed at the time t4, a fourth step S4 performed at the time t5, a fifth step S5 performed at the time t6, a sixth step S6 performed at the time t7, and a seventh step S7 performed at a time t8.
As shown here, the transactions AT1 through AT3 have identical steps thereof performed at respective and different timings. Since the bus is not exclusively occupied by a single transaction, efficient processing can be achieved. In order to take advantage of such pipeline operation, an address-retry mechanism is employed.
In the system as described above, however, when an address transaction continues to be subjected to retry operation many times, a processing time is elongated, resulting in a decrease in processing efficiency. Further, when a predetermined retry count or a predetermined time period is reached, a system is regarded as having a failure, resulting in a system shutdown.
Accordingly, there is a need for an information-processing device, an information-processing method, and a processor that perform retry operation in such a fashion as to make efficient use of a system and to achieve a sufficient reliability.
Accordingly, it is a general object of the present invention to provide an information-processing device, an information-processing method, and a processor that can obviate one or more of the shortcomings of the related art.
It is another and more specific object of the present invention to provide an information-processing device, an information-processing method, and a processor that can perform retry operation in such a fashion as to make efficient use of a system and to achieve a sufficient reliability.
In order to achieve the above objects according to the present invention, an information-processing device includes a bus, a plurality of processors connected to the bus, and a bus-control unit which detects whether an excessively retried address transaction is present. Any given one of the processors includes an issuing unit which issues address transactions, a monitoring unit which communicate with the bus-control unit, and a retry-control unit which controls the issuing unit to suspend issuance of address transactions other than the excessively retried address transaction and to put an already issued address transaction in a status of compulsory retry if the monitoring unit is informed of presence of the excessively retried address transaction by the bus-control unit.
The device described above makes it possible to process the excessively retried address transaction ahead of other address transactions, thereby ensuring that processing will be completed within a predetermined time period. This prevents the system from suffering shutdown.
According to another aspect of the present invention, the information-processing device as described above is such that the retry-control unit detects whether address transactions are of a special type, and allows the issuing unit to issue an address transaction of the special type even if the monitoring unit is informed of the presence of the excessively retried address transaction.
The device described above takes into account address transactions of a special type that do not have to be suppressed or must not be suppressed. Since the retry-control unit allows the issuing unit to issue an address transaction of the special type, the present invention does not interfere with the requirements that address transactions of the special type be not suppressed.
According to another aspect of the present invention, the information-processing device as described above is such that address transactions are classified into groups, and the retry-control unit controls the issuing unit to suspend issuance of new address transactions other than the excessively retried address transaction and to put an already issued address transaction in a status of compulsory retry only if the new address transactions and the already issued address transaction belong to a group that includes the excessively retried address transaction.
In the device described above, the address transactions are grouped, so that the status of excessive retry in a given group affects only the address transactions that belong to the same group. This insures that the status of excessive retry affects only the address transactions within a limited range.